Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device includes a base substrate made of silicon, a cap substrate and a leading electrode having a metal part. The base substrate has base semiconductor regions being insulated and separated from each other at a predetermined portion of a surface layer thereof. The cap substrate is bonded to the predetermined portion of the surface layer of the base substrate. The leading electrode has a first end connected to one of the plurality of base semiconductor regions of the base substrate and extends through the cap substrate such that a second end of the leading electrode is located adjacent to a surface of the cap substrate for allowing an electrical connection with an external part, the surface being opposite to a bonding surface at which the base substrate and the cap substrate are bonded. The leading electrode defines a groove between an outer surface thereof and the cap substrate.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on Japanese Patent Applications No.2009-286874 filed on Dec. 17, 2009 and No. 2010-251092 filed on Nov. 9,2010, the disclosure of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a method ofmanufacturing the same. More particularly, the present invention relatesto a semiconductor device having a cap substrate bonded to a basesubstrate made of silicon for protecting various elements formed in asurface layer of the base substrate, and a method of manufacturing thesame.

BACKGROUND OF THE INVENTION

In a semiconductor device, it is known to bond a cap substrate to a basesubstrate for protecting various element formed in a surface layer ofthe base substrate.

In such a semiconductor device, an electrical connection forelectrically connecting the base substrate and an external part isnecessary. For example, it is known to make a bonding wire directly onthe surface of the base substrate through a through hole formed in thecap substrate. In such a method, however, a large through hole isrequired in the cap substrate to conduct wire bonding. That is, an areanecessary for making the electrical connection is likely to increase.

In order to ease the electrical connection between the element and theexternal part by the wire bonding, soldering or the like in a smallarea, a leading electrode that extends from the base substrate to thesurface of the cap substrate and allows the electrical connection at theend can be employed.

It has been known to use a portion of the cap substrate as the leadingelectrode. For example, the cap substrate made of silicon is dividedinto partial regions by an insulating and separating trench, and aspecific region of the partial regions, which connects to an insulatedand separated base semiconductor region of the base substrate, is usedas a leading conductive region. The upper end of the specific region iselectrically connected to the external part by the wire bonding,soldering or the like.

A semiconductor device having such an electrical connection structureis, for example, described in Japanese Patent Application PublicationsNo. JP2008-229833A (Publication 1, corresponding to US2008/0290490A1)and No. JP2008-256495 (Publication 2).

FIG. 30 shows an example of the semiconductor device described inPublication 1. A semiconductor device 91 shown in FIG. 30 has asemiconductor base substrate B2 and a conductive cap substrate C2 bondedto the base substrate B2.

The base substrate B2 is a SOI (Silicon On Insulator) substrate in whichan embedded oxide film 20 is interposed between a SOI layer 21 and asupport substrate 22. Insulated and separated multiple basesemiconductor regions Bs are formed in a surface layer of the basesubstrate B2. The base semiconductor regions Bs are provided by the SOIlayer 21, and are insulated and separated from adjacencies by a trench23 that reaches the embedded oxide film 20. Projections T1 are formedabove the base semiconductor regions Bs. The projections T1 are providedby a conductive film 50, which is made of poly crystal silicone, metalor the like.

The semiconductor device 91 includes a mechanical quantity sensorelement for measuring a mechanical quantity, such as acceleration andangular velocity, using an inertia force. The mechanical quantity sensorelement is constructed of the multiple base semiconductor regions Bs.Specifically, the base semiconductor regions Bs include at least twobase semiconductor regions Bs1 and two base semiconductor regions Bs2.

The base semiconductor regions Bs1 constitute a movable semiconductorregion. The base semiconductor regions Bs1 are formed by performingsacrifice layer etching on a part of the embedded oxide film 20. Thebase semiconductor regions Bs1 as the movable semiconductor regioninclude a movable electrode Em, which is formed to be displaceable.

The base semiconductor regions Bs2 constitute a fixed semiconductorregion including a fixed electrode Es opposed to the movable electrodeEm. The two base semiconductor region Bs1 and the two base semiconductorregion Bs2 each form a continuous and integrated region on a plane.

In the semiconductor device 91, a capacitance is created between opposedsurfaces of the movable electrode Em and the fixed electrode Es. As themovable electrode Em is displaced in a direction perpendicular to theopposed surfaces in accordance with the applied mechanical quantity, thecapacitance changes in accordance with a change in the distance betweenthe movable electrode Em and the fixed electrode Es. Thus, the appliedmechanical quantity is detected by measuring the change in capacitance.

The cap substrate C2 is provided by a single crystal silicon substrate30 on which multiple cap conductive regions Ce as partial regions areformed. The cap conductive regions Ce are divided by an insulating andseparating trench 31 that passes through the single crystal siliconsubstrate 30. The cap substrate C2 has a surface protection layer 33made of silicon oxide (SiO₂) or the like, and electrode pads 34 made ofaluminum (Al) or the like.

The cap substrate C2 is bonded to the projections T1 formed on the basesemiconductor regions Bs, and a bonding surface D1 is formedtherebetween. The bonding surface D1 has a loop shape in a predeterminedregion R1 of the base substrate B2. Thus, a space sealed in a highlyvacuum condition is provided between the surface of the predeterminedregion R1 and the surface of the cap substrate C2 by bonding the basesubstrate B2 and the cap substrate C2.

Also, as the base substrate B2 and the cap substrate C2 are bonded,specific cap conductive regions Ce1, Ce2 are electrically connected tothe specific base semiconductor regions Bs1, Bs2, respectively, to serveas leading conductive regions. In other words, the leading conductiveregions Ce1, Ce2 are respectively connected to the movable semiconductorregion Bs1 and the fixed semiconductor region Bs2, respectively.

FIG. 31 shows an example of a semiconductor device described inPublication 2. A semiconductor device 92 of FIG. 31 has a semiconductormechanical quantity sensor element for detecting a mechanical quantity,such as acceleration and angular velocity, similar to the semiconductordevice 91 of FIG. 30.

The semiconductor device 92 has a base substrate B3 provided by a Salsubstrate. The SOI substrate includes a support substrate 11 made ofsilicon semiconductor and a poly silicon layer 12 disposed on thesupport substrate 11 through an oxide film 13. Sensing portions Se areformed by the poly silicon layer 12 disposed on the support substrate11.

Similar to the semiconductor device 91 of FIG. 30, the sensing portionsSe include a movable electrode and a fixed electrode. The movableelectrode and the fixed electrode are provided by a beam structure,which is generally used in conventional acceleration sensors and angularvelocity sensors. As the movable electrode is displaced in accordancewith the applied acceleration or angular velocity, the capacitancebetween the movable electrode and the fixed electrode is changed. Avoltage signal indicative of the change in capacitance is produced.

Further, a cap C3 is fixed to the base substrate B3 to surround thesensing portions Se. The cap C3 is bonded to the poly silicon layer 12through an adhesive layer Ds made of a resin adhesive or the like. Thecap C3 is provided with penetrating electrodes Ke. The cap C3 is made ofsilicon semiconductor in which impurities, such as phosphorous (P) andboron (B), are preferably doped so as to have electrical conductivity.

The penetrating electrodes Ke pass through the cap C3 in a direction inwhich a thickness of the cap C3 is measured. The penetrating electrodesKe serve to lead electrical signals from the sensing portions Se, whichare located under the cap C3, to the upper surface of the cap C3. Thepenetrating electrodes Ke are constituted as portions of the cap C3having the electrical conductivity.

Further, the cap C3 is formed with grooves 15, which are referred to asair isolations, on peripheries of the penetrating electrodes Ke. Thegrooves 15 surround the penetrating electrodes Ke, and pass through thecap C3 in the direction in which the thickness of the cap C3 ismeasured.

Thus, the penetrating electrodes Ke and portions of the cap C3 on theperipheries of the penetrating electrodes Ke are insulated by means ofthe grooves 15. That is, the grooves 15 serve as electrically insulatingportions to electrically insulate the penetrating electrodes Ke from theperipheral portions thereof in the cap C3. The penetrating electrodes Keare in contact with the poly silicon layer 12 through connectingelectrodes 51, which are made of aluminum, Al—Si or the like, to makeelectrical connection with the sensing portions Se.

In the semiconductor device 91 of FIG. 30, the cap substrate C2 servesas a sealing cap for protecting the mechanical quantity sensor elementformed in the predetermined region R1 of the surface layer of the basesubstrate B2. The cap conductive regions Ce1, Ce2 of the cap substrateC2, which are electrically connected to the base semiconductor regionsBs1, Bs2 of the base substrate B2, serve as leading conductive regions.

In such a structure, however, the insulating and separating trench 31exist on the peripheries of the leading conductive regions Ce1, Ce2 toisolate the leading conductive regions Ce1, Ce2 from the peripheral capconductive regions. Therefore, parasitic capacitance is produced due tothe insulating and separating trench 31 being an electric substance, andis likely to affect performance of the semiconductor device 91.

In the semiconductor device 92 of FIG. 31, on the other hand, thepenetrating electrodes Ke are electrically insulated from the peripheralportions in the cap C3 by the grooves 15 as the air isolations.Therefore, the electric permittivity at the grooves 15 is smaller thanthat at the trench 31 of the semiconductor device 91 in which theelectric substance is embedded. That is, the semiconductor device 92 ofFIG. 31 is less apt to generate the parasitic capacitance, as comparedwith the semiconductor device 91 of FIG. 30.

The semiconductor device 91 employs the cap substrate C2 made of singlecrystal silicon. The semiconductor device 92 employs the cap substrateC3 made of silicon semiconductor. In general, silicon is less expensivethan other substrate materials, and a trench is easily formed in asilicon substrate. However, silicon has a relatively large specificresistance. Therefore, the leading conductive regions Ce1, Ce2 and thepenetrating electrodes Ke are likely to increase resistance, and hencethe applicable range of such semiconductor devices may be restricted.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductordevice having a base substrate and a cap substrate bonded to the basesubstrate for protesting the base substrate, in which a leadingelectrode for allowing an electrical connection between the basesubstrate and an external part has a structure capable of reducingresistance, and the leading electrode and a neighboring portion thereofhave a structure capable of reducing occurrence of parasiticcapacitance, and a method of manufacturing the semiconductor device.

According to an aspect of the present invention, a semiconductor deviceincludes a base substrate, a cap substrate and a leading electrode forallowing an electrical connection between the base substrate and anexternal device. The base substrate is made of silicon and has aplurality of base semiconductor regions in a predetermined portion of asurface layer thereof. The cap substrate is bonded to the predeterminedportion of the surface layer of the base substrate. The leadingelectrode includes a metal part. The leading electrode passes throughthe cap substrate. A first end of the leading electrode is connected toone of the plurality of base semiconductor regions. A second end of theleading electrode is located adjacent to a surface of the cap substrate,the surface being opposite to a bonding surface at which the basesubstrate and the cap substrate are bonded, to allow the electricalconnection with an external part. Further, a groove is formed betweenthe leading electrode and the cap substrate.

The leading electrode has the metal part having conductivity higher thanthat of silicon. Hence, the resistance at the leading electrode can bereduced, as compared with a conventional semiconductor device. Further,the groove is formed between the leading electrode and the capsubstrate. That is, because the leading electrode has an air isolationstructure, the conventional insulating and separating trench for formingthe leading conductive region is not employed. Therefore, parasiticcapacitance will not be easily created. In addition, stress due to athermal expansion difference between the metal part and the capsubstrate is reduced.

According to a second aspect of the present invention, a method ofmanufacturing a semiconductor device includes: forming a base substratemade of silicon; forming a cap substrate; bonding the cap substrate to apredetermined portion of the base substrate; and forming a leadingelectrode including a metal part. The base substrate has a plurality ofbase semiconductor regions in the predetermined portion of a surfacelayer thereof, and the plurality of base semiconductor regions isinsulated and separated from each other. The leading electrode passesthrough the cap substrate. The leading electrode has a first endconnected to one of the plurality of base semiconductor regions and asecond end located adjacent to a surface of the cap substrate. Theleading electrode defines a groove between an outer surface thereof andthe cap substrate.

In the semiconductor device manufactured by the above method similareffects as described in the above are achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention willbecome more apparent from the following detailed description made withreference to the accompanying drawings, in which like parts aredesignated by like reference characters and in which:

FIG. 1A is a schematic cross-sectional view of a part of a semiconductordevice as an example according to an embodiment of the presentinvention;

FIG. 1B is a schematic cross-sectional view taken along a line IB-IB inFIG. 1A;

FIG. 2 is a perspective view of a base substrate of the semiconductordevice shown in FIGS. 1A and 1B;

FIGS. 3A to 3C are schematic cross-sectional views for showing a processof forming the base substrate shown in FIG. 2;

FIGS. 4A to 4C are schematic cross-sectional views for showing a processof forming a cap substrate of the semiconductor device shown in FIGS. 1Aand 1B;

FIGS. 5A to 5D are schematic cross-sectional views for showing a processof manufacturing the semiconductor device using the base substrate andthe cap substrate formed by the processes shown in FIGS. 3A to 3C and 4Ato 4C;

FIG. 6A is a schematic cross-sectional view of a leading electrodethereof as a modification of a leading electrode of the semiconductordevice shown in FIGS. 1A and 1B.

FIG. 6B is a schematic cross-sectional view of a leading electrode asanother modification of the leading electrode of the semiconductordevice shown in FIGS. 1A and 1B.

FIGS. 7A to 7D and 8A to 8D are schematic cross-sectional views forshowing a process of forming the leading electrodes shown in FIGS. 6Aand 6B;

FIG. 9A is a schematic cross-sectional view of a part of a semiconductordevice as a modification of the semiconductor device shown in FIGS. 1Aand 1B;

FIG. 9B is a schematic cross-sectional view taken along a line IXB-IXBin FIG. 9A;

FIG. 10A is a schematic cross-sectional view of a leading electrode as amodification of a leading electrode of the semiconductor device shown inFIGS. 9A and 9B;

FIG. 10B is a schematic cross-sectional view of a leading electrode as amodification of the leading electrode of the semiconductor device shownin FIGS. 9A and 9B;

FIGS. 11A to 11D are schematic cross-sectional views for showing aprocess of forming the leading electrode shown in FIG. 10B;

FIG. 12A is a schematic cross-sectional view of a leading electrode asfurther another modification of the leading electrode of thesemiconductor device shown in FIGS. 9A and 9B;

FIG. 12B is a schematic cross-sectional view taken along a lineXIIA-XIIA in FIG. 12A;

FIG. 13A is a schematic cross-sectional view of a leading electrode asyet another modification of the leading electrode of the semiconductordevice shown in FIGS. 9A and 9B;

FIG. 13B is a schematic cross-sectional view of a leading electrode asstill another modification of the leading electrode of the semiconductordevice shown in FIGS. 9A and 9B;

FIG. 14A is a schematic cross-sectional view of a part of asemiconductor device as a modification of the semiconductor device shownin FIGS. 9A and 9B;

FIG. 14B is a schematic cross-sectional view of a part of asemiconductor device as another modification of the semiconductor deviceshown in FIGS. 9A and 9B;

FIG. 14C is a schematic cross-sectional view of a leading electrode as amodification of a leading electrode of the semiconductor device shown inFIG. 14B;

FIGS. 15A to 15C are schematic cross-sectional views for showing aprocess of manufacturing the semiconductor device shown in FIG. 14A;

FIGS. 16A to 16D, 17A to 17D and 18A to 18C are schematiccross-sectional views for showing a process of forming the leadingelectrodes shown in FIGS. 14B and 14C;

FIG. 19A is a schematic cross-sectional view of a part of asemiconductor device as a modification of the semiconductor device shownin FIGS. 1A and 1B;

FIG. 19B is a schematic cross-sectional view of a part of asemiconductor device as another modification of the semiconductor deviceshown in FIG. 14B;

FIGS. 20A and 20B are schematic cross-sectional views for showing aprocess of forming a leading electrode of the semiconductor device shownin FIG. 19A;

FIGS. 21A to 21D are schematic cross-sectional views for showing aprocess of forming a leading electrode of the semiconductor device shownin FIG. 19B;

FIG. 22 is a schematic cross-sectional view of a part of a semiconductordevice as further another modification of the semiconductor device shownin FIGS. 1A and 1B;

FIG. 23 is a schematic cross-sectional view of a part of a semiconductordevice as an example of another use of the semiconductor device shown inFIGS. 1A and 18;

FIG. 24 is a schematic cross-sectional view of a part of a semiconductordevice as an example of the semiconductor device according to theembodiment;

FIGS. 25A to 25D and 26A to 26C are schematic cross-sectional views forshowing a process of manufacturing the semiconductor device shown inFIG. 24

FIG. 27 is a schematic cross-sectional view of a part of a semiconductordevice as an example of the semiconductor device according to theembodiment;

FIGS. 28A to 28D and 29A to 29D are schematic cross-sectional views forshowing a process of manufacturing the semiconductor device shown inFIG. 27;

FIG. 30 is a schematic cross-sectional view of a part of a semiconductordevice of a prior art; and

FIG. 31 is a schematic cross-sectional view of a part of a semiconductordevice of another prior art.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENT

FIG. 1A is a schematic plan view of a part of a semiconductor device 100as an example of the semiconductor device according to an embodiment.FIG. 1B is a schematic cross-sectional view taken along a line IB-IB inFIG. 1A. FIG. 1A is also a cross-section taken along a line IA-IA inFIG. 1B. FIG. 2 is a perspective view of a base substrate of thesemiconductor device 100 shown in FIGS. 1A and 1B.

In FIGS. 1A, 1B and 2 like parts which correspond to parts of thesemiconductor devices 91, 92 of FIGS. 30 and 31, are designated withlike reference characters.

Referring to FIGS. 1A and 1B, the semiconductor device 100 has a basesubstrate B4 made of silicon and a cap substrate C4 made of silicon. Thebase substrate B4 and the cap substrate C4 are bonded to each other at abonding surface D1.

The semiconductor device 100 includes a mechanical quantity sensorelement using an inertia force. A sensing portion Se for detectingmechanical quantity such as acceleration and angular velocity is formedin a predetermined region R1 of the base substrate B4.

The cap substrate C4 is formed with a recess 32 b. The cap substrate C4is bonded to the base substrate B4 to oppose the predetermined region R1where the sensing portion Se is formed. Thus, the cap substrate C4 sealsa space defined by the recess 32 b and a trench 23 of the base substrateB4.

The base substrate B4 is a SOI (Silicon On Insulator) substrate havingan embedded oxide film 20, a SOI layer 21 and a support substrate 22.The embedded oxide film 20 is disposed between the SOI layer 21 and thesupport substrate 22. The base substrate B4 has multiple basesemiconductor regions Bs including base semiconductor regions Bs1, Bs2in a surface layer thereof. The base semiconductor regions Bs areprovided by the SOI layer 21. The base semiconductor regions Bs areinsulated and separated from each other by the trench 23 that reachesthe embedded oxide film 20.

The sensing portion Se includes a mechanical quantity sensor element formeasuring acceleration or angular velocity. The mechanical quantitysensor element is constructed of some of the base semiconductor regionsBs.

The base semiconductor region Bs1 is a movable semiconductor regionincluding a movable electrode Em. The movable electrode Em is formed byperforming sacrifice layer etching on a part of the embedded oxide film20. The movable electrode Em is displaceable. The base semiconductorregion Bs2 is a fixed semiconductor region including a fixed electrodeEs that is opposed to the movable electrode Em.

In the semiconductor device 100, capacitance is created between theopposed surfaces of the movable electrode Em and the fixed electrode Es.As the mechanical quantity is applied to the movable electrode Em, themovable electrode Em is displaced in a direction perpendicular to theopposed surfaces. The capacitance changes in accordance with a change ina distance between the opposed surfaces of the movable electrode Em andthe fixed electrode Es. The change in capacitance is measured to detectthe applied mechanical quantity. It is noted that, in the base substrateB4, other elements and circuits may be formed in regions other than thepredetermined region R1.

The cap substrate C4 includes a single crystal silicon 30, which can beprecisely processed at a relatively low cost. In the cap substrate C4,the recess 32 b is formed at a position corresponding to the sensingportion Se of the base substrate B4. An insulating layer 32 a is formedon a lower surface of the single crystal silicon substrate 30 bonded tothe base substrate B4. The insulating layer 32 a is, for example, madeof silicon oxide (SiO₂).

In the semiconductor device 100, as described above, the base substrateB4 and the cap substrate C4 are bonded to each other through the bondingsurface D1. In a semiconductor device having a cap substrate as thesemiconductor device 100, the cap substrate is generally employed toprotect various elements formed in a surface layer of a base substrate.

In the semiconductor device having the cap substrate, as a method offorming an electrical connection between the various elements formed inthe surface layer of the base substrate and external parts, it may bepossible to directly connect a bonding wire to a surface of, the basesubstrate by a wire bonding technique through a through hole formed inthe cap substrate.

In such a method, however, the through hole of the cap substrate needsto be large enough to allow the wire bonding. Thus, an area for makingthe electrical connection is likely to increase.

In order to ease the electrical connection with a small area, asemiconductor device having a cap substrate needs a leading electrodethat extends from the surface of a base substrate to an upper surface ofthe cap substrate to allow the electrical connection with an externalpart at an upper end thereof.

The semiconductor device 100 has a leading electrode De1 that extendsfrom the surface of the base substrate B4 to an upper surface of the capsubstrate C4 for facilitating an electrical connection between themechanical quantity sensor element of the base substrate B4 and theexternal part.

The leading electrode De1 includes a metal part 40 made of metal such asaluminum (Al), copper (Cu), chrome (Cr) tungsten (W), and platinum (Pt).A lower end of the leading electrode De1 is connected to a predeterminedbase semiconductor region Bs. The leading electrode De1 extends from thepredetermined base semiconductor region Bs to the upper surface of thecap substrate C4, while passing through the cap substrate C4. Here,“extending to the upper surface of the cap substrate C4” means that anupper end of the leading electrode De1 is located adjacent to the uppersurface of the cap substrate C4. For example, the upper end of theleading electrode De1 is located at the same height as or higher thanthe upper surface of the cap substrate C4.

A groove 35 is formed on a periphery of the leading electrode De1. Inother words, the groove 35 is formed between an outer surface of theleading electrode De1 and the cap substrate C4. The leading electrodeDe1 is separated from the cap substrate C4 by the groove 35. FIG. 1Bshows a condition where a bonding wire 60 is connected to the upper endof the leading electrode De1.

In the semiconductor device 91 of FIG. 30, the silicon cap substrate C2is divided into partial regions Ce through the insulating and separatingtrench 31, and predetermined conductive regions Ce1, Ce2 of the partialregions Ce, which connect to the insulated and separated basesemiconductor region Bs, are used as the leading conductive regions tomake electrical connections at the upper end thereof with the externalparts by wire bonding, soldering or the like.

In the semiconductor device 92 of FIG. 31, the penetrating electrodesKe, which are provided by portions of the silicon cap substrate C3 andseparated through the grooves 15, are used to make electricalconnections at the upper end thereof with the external parts by the wirebonding, soldering or the like.

In such structures, however, since the resistance of the siliconconductive regions and the silicon penetrating electrodes Ke is large,the applicable ranges of the semiconductor devices are likely to berestricted.

In the semiconductor device 100, on the other hand, the leadingelectrode De1 is provided by the metal part 40, which has high electricconductivity. The metal part 40 connects to the predetermined basesemiconductor region Bs, that is, at a bonding portion Des shown by adashed line in FIG. 2. The metal part 40 passes through the capsubstrate C4, and the upper end of the metal part 40 is located higherthan the upper surface of the cap substrate C4. Therefore, theresistance of the leading electrode De1 is smaller than the resistanceof the conductive regions Ce1, Ce2 and the penetrating electrodes Ke ofthe semiconductor devices 91, 92, which utilize portions of the siliconecap substrates C2, C3. Accordingly, the applicable range of thesemiconductor device 100 increases.

Further, the groove 35 is provided between the leading electrode De1 andthe cap substrate C4. That is, the leading electrode De1 has a so-calledair isolation structure. The cap substrate C4 of the semiconductordevice 100 does not have the insulating and separating trench 31 forforming the partial regions Ce as the semiconductor device 91.

In the semiconductor device 100, therefore, parasitic capacitance willnot be easily formed due to the electric substance such as theinsulating and separating trench 31. Further, since the groove 35 isformed around the leading substrate de1, stress due to a thermalexpansion difference between the leading electrode De1 and the capsubstrate C4 can be reduced.

In the semiconductor device 92 of FIG. 31, since the groove 15 is formedaround the penetrating electrode Ke, the parasitic capacitance will notbe easily formed. In the semiconductor device 92 of FIG. 31, the groove15 reaches the base substrate B3. In the semiconductor device 100 ofFIGS. 1A and 1B, on the other hand, the insulating layer 32 a is formedunder the groove 35, and thus the groove 35 does not reach the basesubstrate B4.

In view of reducing the parasitic capacitance, the groove 15 passingthrough the cap substrate C3 and reaching the base substrate B3 ispreferable as in the semiconductor device 92 of FIG. 31. Thus, it may bepossible to form the groove 35 to reach the base substrate B4 in thesemiconductor device 100.

In the semiconductor device 100, however, the insulating layer 32 a ispositioned at the bottom of the groove 35. That is, the insulating layer32 a is exists around the base of the leading electrode De1. Therefore,the insulating layer 32 a serves as a support portion to increase thestrength of the leading electrode De1, which is particularly requiredduring the wire bonding or soldering the upper end of the leadingelectrode De1.

In the example shown in FIG. 1B, the upper end of the leading electrodeDe1 is located higher than the upper surface of the cap substrate C4. Ascompared with a case where the upper end of the leading electrode De1 isat the same height as or lower than the upper surface of the capsubstrate C4, interference with peripheral portions is reduced.Therefore, the wire bonding and the soldering are easily conducted atthe upper end of the leading electrode De1.

Accordingly, in the semiconductor device 100, the resistance of theleading electrode De1 is reduced and the parasitic capacitance will notbe easily formed around the leading electrode De1.

As described above, the cap substrate C4 is provided by the singlecrystal silicon substrate 30, which is easily processed at a relativelylow cost. Further, since the leading electrode De1 is constructed of themetal part 40, the cap substrate C4 can be provided by a poly crystalsubstrate, an intrinsic silicon substrate in which glass and impuritiesare not doped, or other similar insulating substrates, in place of thesingle crystal silicon substrate.

Next, a method of manufacturing the semiconductor device 100 will bedescribed.

FIGS. 3A-3C are schematic cross-sectional views for showing a process offorming the base substrate B4.

In FIG. 3A, a SOI substrate B4 a including the embedded oxide film 20between the SOI layer 21 and the support substrate 22 is prepared. TheSOI substrate B4 a is formed by a substrate bonding technique, forexample. The embedded oxide film 20 is a silicon oxide (SiO₂) film, andthe support substrate 22 is a single crystal silicon substrate having aspecific resistance in a range of 0.001 to 1 Ωcm, for example.

The SOI layer 21 is used for forming various elements. The SOI layer 21is a single crystal silicon layer containing N+ type impurities such asarsenic (As) and phosphorous (P) with a specific resistance of 0.001 to1 Ωcm and a thickness of 1 to 50 μm. For example, the SOI layer 21 has athickness of 10 to 20 μm, and the SOI layer 21 and the support substrate22 are formed by bonding N+ type single crystal substrates containingimpurities at high concentrations.

In the case where the base semiconductor regions Bs are partly used asthe movable semiconductor region Bs1 including the movable electrode Emand the fixed semiconductor region Bs2 including the fixed electrode Es,it is preferable that the concentration of impurities of the SOI layer21 is as high as possible, that is, the specific resistance of the SOIlayer 21 is as small as possible. In the above-described example, theSOI layer 21 contains the N+ type impurities. As another example, allthe impurities can be P+ type impurities, such as born (B).

In FIG. 3B, a mask pattern (not shown) of such as a photoresist and anoxide film is formed on the SOI layer 21. A trench 23 that hassubstantially perpendicular walls and reaches the oxide film 20 isformed by photolithography and deep-etching techniques. By the trench23, the SOI layer 21 is divided to form the multiple base semiconductorregions Bs, which are insulated and separated from adjacencies, in asurface layer of the SOI substrate B4 a.

In FIG. 3C, after the mask pattern is removed from the SOI layer 21, theembedded oxide film 20 is partly removed through the trench 23 by anetching technique with hydrogen fluoride (HF) gas. Thus, the movablesemiconductor region Bs1 including the movable electrode Em, the fixedsemiconductor region Bs2 including the fixed electrode Es, and the likeare formed. In this case, the portions of the oxide film 20 under themovable electrode Em and the fixed electrode Es are thoroughly removed,as shown in FIG. 3C.

In this way, the base substrate B4 for the semiconductor device 100 isformed.

FIGS. 4A to 4C are schematic cross-sectional views for showing a processof forming the cap substrate C4.

In FIG. 4A, the single crystal silicon substrate 30 is prepared. In FIG.4B, a mask pattern (not shown) of such as a photoresist or an oxide filmis formed on a lower surface of the silicon substrate 30. Then, therecess 32 b is formed by photolithography and etching techniques.

In FIG. 4C, the insulating layer 32 a of the silicon oxide (SiO₂) isformed on the lower surface of the silicon substrate 30 by a thermaloxidation technique. In this way, the cap substrate C4 for thesemiconductor device 100 is formed.

FIGS. 5A to 5D are schematic cross-sectional views for showing processof manufacturing the semiconductor device 100 using the base substrateB4 and the cap substrate C4 respectively formed by the processes shownin FIGS. 3A to 3C and FIGS. 4A to 4D.

As shown in FIGS. 5A and 5B, the base substrate B4 and the cap substrateC4 are bonded to each other.

Specifically, in FIG. 5A, the cap substrate C4 is positioned relative tothe base substrate B4 such that the cap substrate C4 is opposed to thepredetermined region R1 where the mechanical quantity sensor element hasbeen formed, and is laid on the base substrate B4.

In FIG. 5B, the lower surface of the cap substrate C4 is bonded to theupper surface of the base substrate B4. Here, the cap substrate C4 andthe base substrate B4 are bonded using an arbitrary adhesive. Thus, thecap substrate C4 and the base substrate B4 are securely bonded at thebonding surface D1, and the space defined by the recess 32 b and thetrench 23 is fully sealed.

Next, the leading electrode De1 is formed, as shown in FIGS. 5B to 5D.

First, as shown in FIG. 5B, a trench 41 is formed at a predeterminedposition of the cap substrate C4. In this case, the trench 41 is formedto reach the predetermined base semiconductor region Bs of the basesubstrate B4.

In FIG. 5C, the metal part 40 is embedded in the trench 41, and then anupper surface of the cap substrate C4 is etched so that the upper end ofthe metal part 40 becomes higher than the upper surface of the capsubstrate C4.

In FIG. 5D, a portion of the silicon substrate 30 around the trench 41in which the metal part 40 is embedded is etched to form the groove 35around the trench 41.

In this way, the leading electrode De1 is formed, and the semiconductordevice 100 is manufactured. It is noted that, in an actual manufacturingprocess, the base substrate B4 and the cap substrate C4 are prepared inthe condition of wafers, and the finished semiconductor devices 100 areproduced by cutting the wafers into multiple chips after the process ofFIGS. 5A to 5D.

Next, modifications of the leading electrode De1 and a neighboringstructure thereof will be described in detail.

FIG. 6A is a schematic cross-sectional view of the leading electrode De1and the neighboring structure thereof as a modification. FIG. 6B is aschematic cross-sectional view of the leading electrode De1 and theneighboring structure thereof as another modification.

In the modification shown in FIG. 6A, an insulating layer 42 is formedat the bottom portion of the groove 35 a. The insulating layer 42 isseparate from the insulating layer 32 a, and has a thickness greaterthan a thickness of the insulating layer 32 a. In this case, therefore,strength of the leading electrode De1 required for forming theelectrical connection to the external part, that is, for conducting thewire bonding and the soldering, can be increased, as compared with astructure shown in FIG. 1B.

In the modification shown in FIG. 5B, a groove 35 b is formed around theleading electrode De1. The groove 35 b reaches the base substrate B4,similar to the structure around the penetrating electrode Ke of thesemiconductor device 92 shown in FIG. 31. In this case, therefore,parasitic capacitance due to the leading electrode De1 can be furtherreduced, as compared with the structures shown in FIGS. 1B and 6A.

FIGS. 7A to 7D and 8A to 8D are schematic cross-sectional views forshowing a process of forming the structures shown in FIGS. 6A and 6B.The process shown in FIGS. 7A to 7D and 8A to 8D is performed after thebase substrate B4 and the cap substrate C4 are bonded in the mannershown in FIGS. 5A and 5B.

In FIG. 7A, a silicon nitride (Si₃N₄) film 30 a is formed on the singlecrystal silicon substrate 30 of the cap substrate C4 by a low pressurechemical vapor deposition (LPCVD) technique or a plasma chemical vapordeposition (CVD) technique. The silicon nitride film 30 a can be formedon the single crystal silicon substrate 30 before the cap substrate C4is bonded to the base substrate B4.

In FIG. 7B, a mask pattern (not shown) of a photoresist is formed on thesilicon nitride film 30 a, and then a trench 41 a is formed at apredetermined position of the cap substrate C4 by etching from the topof the silicon nitride film 30 a. The trench 41 a is formed to reach thepredetermined base semiconductor region Bs.

In FIG. 7C, a silicon oxide film 42 a is deposited on an entire surface,that is, on the silicon nitride film 30 a and walls of the trench 42 aby a plasma CVD technique.

In FIG. 7D, the silicon oxide film 42 a formed on the silicon nitridefilm 30 a and the bottom wall of the trench 41 a is removed. Thus, thesilicon oxide film 42 a on the side wall of the trench 41 a remains.

Next, in FIG. 8A, a metal layer 40 a, which is for example made ofaluminum (Al), is deposited on an entire surface, that is, on thesilicon nitride film 30 a and inside of the trench 41 a. The trench 41 ais filled with the metal layer 40 a.

In FIG. 8B, the metal layer 40 a on the silicon nitride film 30 a isremoved by an etchback technique. Thus, the metal layer 40 a inside ofthe trench 41 a remains to form the metal part 40 of the leadingelectrode De1 of FIGS. 6A and 6B.

In FIG. 8C, the groove 35 a is formed by removing the silicon oxide film42 a formed on the side wall of the trench 41 a. The silicon oxide film42 a remains at a lower portion of the groove 35 a. Thus, the insulatinglayer 42 shown in FIG. 6A is formed.

In this way, the leading electrode De1 and its neighboring portion shownin FIG. 6A are formed.

The leading electrode De1 and its neighboring portion shown in FIG. 6Bare formed by entirely removing the silicon oxide film 42 a from theside walls of the trench 41 a, as shown in FIG. 8D.

As described in the above, after a bonding step shown in FIG. 7A, trenchforming step for forming the trench 41 a in the cap substrate C4 toreach the predetermined base semiconductor region Bs is performed. In asubsequent leading electrode forming step, the meal layer 40 a isembedded in the trench 41 a to form the metal part 40 of the leadingelectrode De1. Then, the groove 35 a, 35 b is formed at portions of thetrench 41 a.

FIG. 9A is a schematic plan view of a part of a semiconductor device 110as a modification of the semiconductor device 100 shown in FIGS. 1A and1B. FIG. 9B is a schematic cross-sectional view taken along a lineIXB-IXB in FIG. 9A. FIG. 9A is also a schematic cross-sectional viewtaken along a line IXA-IXA in FIG. 9B. In the semiconductor device 110shown in FIGS. 9A and 9B, like parts are denoted by like referencecharacters as those of the semiconductor device 100 shown in FIGS. 1Aand 1B.

As shown in FIGS. 9A and 9B, the semiconductor device 110 has the samebase substrate B4 as that of the semiconductor device 100 of FIGS. 1Aand 1B. With regard to a cap substrate C5 of the semiconductor device110, a leading electrode De2 and its neighboring structure are differentfrom the leading electrode De1 and its neighboring structure of the capsubstrate C4 of the semiconductor device 100

The leading electrode De1 of the semiconductor device 100 is constructedof only the metal part 40. Further, although the groove 35 is formedbetween the cap substrate C4 and the leading electrode De1, the capsubstrate C4 is constructed of a single member, that is, the siliconsubstrate 30.

With regard to the cap substrate C5 of the semiconductor device 110, onthe other hand, a groove 36 is formed in the single crystal siliconsubstrate 30 to divide the single crystal silicon substrate 30 into aportion surrounding the leading electrode De2 and its peripheralportion. That is, the cap substrate C5 is divided into multiple partialregions Cs by the grooves 36. The partial regions Cs are insulated andseparated by the grooves 36. The leading electrode De2 is constructed ofa predetermined partial region Cs1 and the metal part 40 formed in thepredetermined partial region Cs1.

Similar to the semiconductor device 100 of FIGS. 1A and 1B, the leadingelectrode De2 of the semiconductor device 110 has the metal part 40 thatcontacts the base semiconductor region Bs and extends to the uppersurface of the cap substrate C5. As such, the resistance of the leadingelectrode De2 is reduced, as compared with that in the semiconductordevices 91, 92 of FIGS. 30, 31. With this, the applicable rangeincreases.

The groove 36 is formed between the leading electrode De2 and the capsubstrate C5, similar to the semiconductor device 100 of FIGS. 1A and 1BTherefore the parasitic capacitance will not be easily formed on aperiphery of the leading electrode De2.

The leading electrode De2 of the semiconductor device 110 is differentfrom the leading electrode De1 of the semiconductor device 100 since theleading electrode De2 includes the predetermined partial region Cs1 asan element in addition to the metal part 40. The predetermined partialregion Cs1 is formed around the metal part 40, but is insulated andseparated from the adjacent partial portion Cs by the groove 36.

In the semiconductor device 110, therefore, the resistance can bereduced by the metal part 40 as the element of the leading electrodeDe2. Furthermore, because the predetermined partial region Cs1 aroundthe metal part 40 serves as a support part, strength of the leadingelectrode De2 required at the time of wire bonding and soldering can beincreased.

In the case where the cap substrate C5 is divided into multiple partialregions Cs, which are insulated and separated from each other, as thesemiconductor device 110, integrated circuits (IC circuits) can beformed in other partial regions Csa, Csb of the partial regions Cs, asshown in FIG. 9A.

FIGS. 10A and 10B are schematic cross-sectional views of the leadingelectrode De2 and the neighboring portion thereof as modifications ofthe structure shown in FIGS. 9A and 9B.

In the modification shown in FIG. 10A, a groove 36 a is formed to passthrough the cap substrate C5 and reach the base substrate B4, similar tothe groove 35 b shown in FIG. 6B. Therefore, in the structure shown inFIG. 10A parasitic capacitance due to the leading electrode De2 isfurther reduced, as compared with the structure shown in FIGS. 9A and9B.

In the modification shown in FIG. 10B, the silicon nitride film 30 aremains, which has been formed at the beginning of the forming of theleading electrode De2 as shown in FIG. 7A, on the single crystal siliconsubstrate 30. Further, the upper end of the metal part 40 is on the sameheight as the upper surface of the silicon nitride film 30 a. That is,the silicon nitride film 30 a is formed above the predetermined partialregion Cs1 formed around the metal part 40, and the upper surface of thesilicon nitride film 30 is coplanar with the upper surface of the metalpart 40.

In such a structure, because the silicon nitride film 30 a serves as asupport portion, strength of the leading electrode De2 required at thetime of wire bonding and soldering is increased, as compared with thatof the leading electrode shown in FIG. 10A.

FIGS. 11A to 11D are schematic cross-sectional views for showing aprocess of forming the leading electrode De2 and its neighboringstructure shown in FIG. 10B.

The process begins from the similar condition shown in FIG. 7A after thebase substrate B4 and the cap substrate C5 are bonded. As shown in FIG.11A, a mask pattern (not shown) of a photoresist is formed on thesilicon nitride film 30 a, and then a trench 41 a is formed at apredetermined position of the cap substrate C5 by etching from the topof the silicon nitride film 30 a. The trench 41 a is formed to reach thepredetermined base semiconductor region Bs.

In FIG. 11B the metal layer 40 a is deposited on an entire surface, thatis, over the silicon nitride film 30 a and inside of the trench 41 a.Thus, the trench 41 b is filled with the metal layer 40 a.

In FIG. 11C, the metal layer 40 a above the silicon nitride film 30 a isremoved by an etchback technique. The metal layer 40 a inside of thetrench 41 b remains to form the metal part 40 of the leading electrodeDe2 shown in FIG. 10B.

In FIG. 11D, a mask pattern (not shown) of a photoresist is formed onthe silicon nitride film 30 a, and the groove 36 a is formed by etchingfrom the top of the mask pattern.

In this way, the leading electrode De2 and its neighboring structureshown in FIG. 10B are formed. It is noted that the leading electrode De2and its neighboring structure shown in FIG. 10A are formed by removingthe silicon nitride film 30 a after the step shown in FIG. 11D. It isalso noted that the leading electrode De2 and its neighboring structureshown in FIG. 9B are formed by forming the groove 36 a while remainingthe insulating layer 32 a at the bottom of the groove 36 a in the stepof FIG. 11D and further removing the silicon nitride film 30 a after thestep of FIG. 11D.

FIG. 12A is a plan view of the leading electrode De2 and the neighboringstructure thereof as further another modification of the structure shownin FIGS. 9A and 9B. FIG. 12B is a schematic cross-sectional view takenalong a line XIIB-XIIB in FIG. 12A. FIG. 12A is also across-sectiontaken along a line XIIA-XIIA in FIG. 12B.

A cap substrate C10 shown in FIGS. 12A and 12B includes an insulatingsubstrate 30 z made of intrinsic silicon in which impurities are notdoped. That is, the cap substrate C10 is different from the capsubstrate C5 of FIGS. 9A, 9B, 10A and 10B, which includes the singlecrystal silicon substrate 30 in which the impurities are doped.

Further, as shown in FIG. 12A, a groove 36 b having a substantiallyC-shape is formed around the metal part 40 of the leading electrode De2.A portion of the substrate 30 z formed around the metal, part 40 isconnected to an adjacent portion of the substrate 30 z, that is, on aperiphery of the groove 36 b through an opening of the C-shape of thegroove 36 b.

Therefore, in the structure shown in FIGS. 12A and 12B, strength of theleading electrode De2 required at the time of wire bonding and solderingis further increased, as compared with the structures shown in FIGS. 9A,9B and 10A. Since the substrate 30 z has an insulating property, themetal part 40 of the leading electrode De2 is electrically insulatedfrom a peripheral portion.

FIGS. 13A and 13B are schematic cross-sectional views of a leadingelectrode De3 and a neighboring structure thereof as still othermodifications of the structure shown in FIGS. 9A and 9B.

The leading electrodes De3 shown in FIGS. 13A and 13B are provided bysubdividing the leading electrodes De2 of FIGS. 10A and 10B,respectively. That is, the metal part 40 is constructed of multipleportions in a predetermined partial region Cs2, which is one of thepartial regions Cs and separated and insulated from a peripheral partialregion Cs by the groove 36 a.

In the structure shown in FIG. 13A, the silicon nitride film 30 a formedabove the single crystal silicon substrate 30 during the manufacturingprocess is removed. In the structure shown in FIG. 13B, the siliconnitride film 30 a remains on the single crystal silicon substrate 30.

In the structures shown in FIGS. 13A and 13B, stress due to a thermalexpansion difference between the metal part 40 and the partial regionCs2 made of silicon is further reduced, as compared with the structuresshown in FIGS. 10A and 10B.

In the structure shown in FIG. 13A, at the time of wire bonding orsoldering, the bonding wire 60 and the solder can be embedded betweenthe divided portions of the metal part 40, which protrude higher thanthe upper surface of the partial region Cs2. Therefore, reliability ofconnection improves.

FIG. 14A is a schematic cross-sectional view of a part of asemiconductor device 111 as a modification of the semiconductor device110 shown in FIGS. 9A and 9B. FIG. 14B is a schematic cross-sectionalview of a part of a semiconductor device 112 as another modification ofthe semiconductor device 110 shown in FIGS. 9A and 9B. FIG. 14C is aschematic cross-sectional view of a leading electrode De5 and itsneighboring structure as a modification of a leading electrode De5 andits neighboring structure of the semiconductor device 112 shown in FIG.14B.

The base substrates B4 of the semiconductor devices 111, 112 are thesame as the base substrates B4 of the semiconductor devices 100, 110 ofFIGS. 1A, 1B, 9A and 9B. The semiconductor devices 111, 112 have capsubstrates C7, C8 and leading electrodes De4, De5, which have differentstructures from the cap substrates C5 and the leading electrode De2 ofthe semiconductor device 110 of FIGS. 9A and 9B.

The leading electrode De2 of the semiconductor device 110 is constructedof the predetermined partial region Cs1 and the metal part 40 formed atthe center of the partial region Cs1. On the other hand, the leadingelectrode De4 of the semiconductor device 111 is constructed of apredetermined partial region Cs3, which is one of the partial regionsCs, and the metal part 40 that covers a side wall and an upper surfaceof the partial region Cs3.

That is, in the leading electrode De4 of the semiconductor device 111,since the metal part 40 covers the upper surface of the partial regionCs4, connecting area between the metal part 40 and the bonding wire orthe solder is increased, as compared with the leading electrode De2 ofthe semiconductor device 110 shown in FIGS. 9A and 9B in which the metalpart 40 does not cover the upper surface of the partial region Cs1.Therefore, the electrical connection further improves.

The leading electrode De5 of the semiconductor device 112 is constructedof the predetermined partial region Cs4 and the metal part 40 covering alower surface of the partial region Cs4 in addition to the side wall andthe upper surface of the partial region Cs4. In this case, theconnection between the leading electrode De5 and the predetermined basesemiconductor region Bs of the base substrate B4 further improves, ascompared with the connection between the leading electrode De4 and thepredetermined base semiconductor region Bs of the semiconductor device111 shown in FIG. 14A.

The metal part 40 of the leading electrode De4 of the semiconductordevice 111 connects to the base semiconductor region Bs and extends tothe same height as or higher than the upper surface of the cap substrateC7. Similarly, the metal part 40 of the leading electrode De5 of thesemiconductor device 112 connects to the base semiconductor region Bsand extends to the same height as or higher than the upper surface ofthe cap substrate C8. As such, in the semiconductor devices 111, 112,resistance of the leading electrodes De4, De5 is reduced, as comparedwith that of the semiconductor devices 91, 92 of FIGS. 30 and 31.Therefore, the applicable ranges of the semiconductor devices 111, 112increase.

In addition, in the semiconductor device 111 of FIG. 14A, a groove 37 ais formed between the leading electrode De4 and the cap substrate C7.Therefore parasitic capacitance will not be easily formed on a peripheryof the leading electrode De4.

Likewise in the semiconductor device 112 of FIG. 14B, a groove 37 b isformed between the leading electrode De5 and the cap substrate C8.Therefore, parasitic capacitance will not be easily formed on aperiphery of the leading electrode De5.

In the leading electrode De5 and the neighboring structure thereof shownin FIG. 14C, a groove 37 c is formed around the leading electrode De5,and an insulating layer 43, which is separate from the insulating layer32 a of the cap substrate C8, is formed at the bottom portion of thegroove 37 c. Therefore, strength of the leading electrode De5 of FIG.140 required at the time of wire bonding and soldering is increased, ascompared with that of the leading electrode De5 of FIG. 14B.

FIGS. 15A to 15C are schematic cross-sectional views for showing aprocess of forming the semiconductor device 111 of FIG. 14A.

In FIG. 15A, after the base substrate B4 and the cap substrate C7 arebonded to each other in a similar manner as shown in FIGS. 5A and 5B,the groove 37 a is formed at a predetermined position of the capsubstrate C7 to reach the insulating layer 32 a. Thus, the singlecrystal silicon substrate 30 is divided into the partial regions Csincluding a partial region Cs3.

In FIG. 15B, the insulating layer 32 a at the bottom portion of thegroove 37 a is further etched to form a trench 41 c reaching thepredetermined base semiconductor region Bs of the base substrate B4.

In FIG. 15C, the metal part 40 is formed successively inside the trench41 c, on the side wall of the partial region Cs3, and on an uppersurface of the partial region Cs3.

In this way, the leading electrode De4 is formed, and thus thesemiconductor device 111 of FIG. 14A is manufactured.

FIGS. 16A to 16D, 17A to 17D and 18A to 180 are schematiccross-sectional views for showing a process of forming the leadingelectrodes De5 and neighboring structures thereof shown in FIGS. 14B and14C.

The process of forming the leading electrode De5 of the semiconductordevice 112 shown in FIG. 14B is different from the processes of formingthe leading electrodes De1 to De4. To form the leading electrode De5 ofthe semiconductor device 112 shown in FIG. 14B necessary structures areformed in the cap substrate C8 before the base substrate B4 and the capsubstrate C8 are bonded to each other.

In FIG. 16A, the single crystal silicon substrate 30 is prepared. A maskpattern (not shown) of a photoresist is formed on the single crystalsilicon substrate 30, and then a trench 41 d is formed by etching fromthe top.

In FIG. 16B, a metal layer 40 b made of such as aluminum (Al) isdeposited entirely over the single crystal silicon substrate 30including the trench 41 d.

In FIG. 16C, a silicon oxide (SiO₂) film 43 a is deposited entirely overthe metal layer 40 b by a plasma CVD technique.

In FIG. 16D, the silicon oxide film 43 a is removed by an etchbacktechnique so that the metal layer 40 b on the surface of the singlecrystal silicon substrate 30 exposes, and only, the silicon oxide film43 a inside of the trench 41 d remains.

Next, in FIG. 17A, a predetermined mask pattern (not shown) is formed,and the metal layer 40 b is partly removed by an etching technique.

In FIG. 17B, the single crystal silicon substrate 30 is turned upsidedown, and then is grinded from the top so that the silicon oxide film 43a embedded inside of the trenches 41 d is exposed. In this way, thesingle crystal silicon substrate 30 is divided to form the insulated andseparated multiple partial regions Cs including a partial region Cs4.

In FIG. 17C, a metal layer 40 c made of such as aluminum (Al) isdeposited entirely over the single crystal silicon substrate 30.

In FIG. 17D, a predetermined mask pattern (not shown) is, formed on themetal layer 40 c, and then the metal layer 40 c is partly removed byetching. Thus, the metal part 40 that covers the side wall, the uppersurface and the lower surface of the partial region Cs4 is formed.

By the above steps, the cap substrate C8 before being bonded is formed.

Next, in FIG. 18A, the base substrate B4 and the cap substrate C8, whichhave been formed beforehand, are bonded to each other.

In FIG. 18B, the trench 37 c is formed by etching the silicon oxide film43 a from the top. The silicon oxide film 43 a remains at the bottom ofthe trench 37 c to provide the insulating layer 43.

By the above steps, the leading electrode De5 and its neighboringstructure shown in FIG. 14C are formed.

If the silicon oxide film 43 a is fully removed by the etching, thegroove 37 b is formed as shown in FIG. 18C. Thus, the leading electrodeDe5 and its neighboring structure shown in FIG. 14B are formed.

As described in the above, the leading electrode forming process can bepartly conducted during the cap substrate forming process. That is, theleading electrode De5 can be formed in a condition of being connected tothe cap substrate C8 while the cap substrate C8 is formed. Then, thelower surface of the leading electrode De5 is connected to thepredetermined base semiconductor region Bs while the cap substrate C8 isbonded to the base substrate B4. Thereafter, the grooves 37 b, 37 c areformed.

FIG. 19A is a schematic cross-sectional view of a part of asemiconductor device 113 as a modification of the semiconductor device100 shown in FIGS. 1A and 1B. FIG. 19B is a schematic cross-sectionalview of a part of a semiconductor device 114 as a modification of thesemiconductor device 112 shown in FIG. 14B.

In the semiconductor device 113 shown in FIG. 19A, a leading electrodeDe6 has an upper surface to which the electrical connection is formedsuch as by the wire bonding and the soldering. The upper surface has anarea greater than that of a lower surface, which is connected to thebase semiconductor region Bs to form the bonding portion Des. Similarly,a leading electrode De7 of the semiconductor device 114 shown in FIG.19B has an upper surface with an area greater than a lower surfacethereof.

In such cases, a pad area increases, as compared with a case where theupper surface of a leading electrode has an area smaller than or thesame as an area of the lower surface thereof. Therefore, the wirebonding and the soldering to the upper surface of the leading electrodesDe6, De7 are easily conducted.

FIGS. 20A and 20B are schematic cross-sectional views for showing aprocess of forming the leading electrode De6 and its neighboringstructure of the semiconductor device 113 shown in FIG. 19A.

As shown in FIG. 20A, the process begins from the condition shown inFIG. 8A. In FIG. 20A, the metal layer 40 a formed on the silicon nitridefilm 30 a is etched in a predetermined pattern so that the metal part 40having the upper surface with the greater area than its lower surface isformed.

In FIG. 20B, the silicon oxide film 42 a on the side wall of the trench41 a and the silicon nitride film 30 a on the single crystal siliconsubstrate 30 are removed in a predetermined order to form the groove 35b.

In this way, the leading electrode De6 and its neighboring structure ofthe semiconductor device 113 shown in FIG. 19A are formed.

FIGS. 21A to 21D are schematic cross-sectional views for showing aprocess of forming the leading electrode De7 and its neighboringstructure of the semiconductor device 114 shown in FIG. 19B.

As shown in FIG. 21A, the process begins from the condition shown inFIG. 17B. In FIG. 21A, the metal layer 40 c made of such as aluminum(Al) is deposited over an entire surface of the single crystal siliconsubstrate 30 with a thickness greater than a thickness of the metallayer 40 c of FIG. 17C

In FIG. 21B, the metal layer 40 c is etched in a predetermined pattern.Thus, the metal part 40 having the upper surface with the greater areathan that of the lower surface is formed.

In FIG. 21C, the base substrate B4 and the cap substrate C8, which havebeen prepared beforehand are bonded to each other.

In FIG. 21D the silicon oxide film 43 a is fully removed by an etchingtechnique to form the groove 37 b.

In this way, the leading electrode De1 and its neighboring structure ofthe semiconductor device 114 shown in FIG. 19B is formed.

FIG. 22 is a schematic cross-sectional view of a part of a semiconductordevice 115 as further another modification of the semiconductor device100 shown in FIGS. 1A and 1B.

The semiconductor device 115 shown in FIG. 22 has an integrated circuit(IC circuit) 101 on a partial region Csc of the single crystal siliconsubstrate 30 in addition to the structure of the semiconductor device100 shown in FIG. 1B. The partial region Csc is one of the partialregions Cs of the cap substrate C4, and seals the sensing portion Se ofthe base substrate B4. In the case where the single crystal siliconsubstrate is used for the cap substrate, in this way, the integratedcircuit can be formed in the predetermined partial region of the capsubstrate, which is insulated and separated.

FIG. 23 is a schematic cross-sectional view of a part of thesemiconductor device 100 for showing another applicable example.

In the example shown in FIG. 1B, the upper end of the leading electrodeDe1 is exemplarily connected to the wire bonding 60 to be electricallyconnected to an external part. In the example shown in FIG. 23, on theother hand, the semiconductor device 100 is mounted to a separate singlecrystal silicon substrate 70 having an integrated circuit (IC circuit)IC2 by a flip-chip technique. The end surfaces of the metal parts 40constructing the leading electrodes De1 are electrically connected topad electrodes 71 formed on the single crystal silicon substrate 70 bysolders 61. In this way, the electrical connections of the end surfacesof the leading electrodes De1 to the external parts can be formed byeither the wire bonding or the soldering.

FIG. 24 is a schematic cross-sectional view of a part of a semiconductordevice 120 as an example of the semiconductor device according to theembodiment. The semiconductor device 120 has two base substrates B5, B6and a cap substrate C9. The base substrates B5, B6 are bonded onopposite sides of the cap substrate C9.

For example, the base substrate B5 is provided with an angular velocitysensor element (a gyro sensor element). The base substrate B6 isprovided with an acceleration sensor element.

In the semiconductor device 120 shown in FIG. 24, the base substrate B5and the second substrate B6 are electrically connected to each otherthrough leading electrodes De8 formed in the cap substrate C9. Althoughthe semiconductor device 120 carries the angular velocity sensor elementand the acceleration sensor element, it is configured compact and wiringresistance of the semiconductor device 120 is reduced.

The cap substrate C9 has a groove 38 formed to divide the single crystalsilicon substrate 30. That is, the cap substrate C9 is divided intomultiple partial regions Cs, which are insulated and separated from eachother, by the groove 38. The leading electrode De8 is constructed of thepredetermined partial region Cs5 of the partial regions Cs and the metalpart 40 formed around the partial region Cs5. For example, the metalpart 40 is formed on the side wall of the partial region Cs5.

The metal part 40 connects to the base semiconductor region Bs andextends to the upper surface of the cap substrate C9. For example, boththe end surfaces of the metal part 40 are on the same heights as theopposite surfaces of the cap substrate C9 and connect to the basesemiconductor regions Bs of the base substrates 85, B6.

Also in such a case, resistance of the leading electrode De8 is reduced,and thus the applicable range, of the semiconductor device 120increases. Further, the groove 38 is formed between the leadingelectrode De8 and the cap substrate C9. Thus, parasitic capacitance willnot be easily formed on a periphery of the leading electrode De8.

FIGS. 25A to 25D and FIGS. 26A to 26C are schematic cross-sectionalviews for showing a process of manufacturing the semiconductor device120 shown in FIG. 24.

In FIG. 25A, the base substrate B5 having the angular velocity sensorelement is formed.

In FIG. 25B, a primary cap substrate C9 a having a primary leadingelectrode De8 a, which will be the leading electrode De8, is formed. Forexample, a primary groove 38 a is formed in the single crystal siliconsubstrate 30 of the primary cap substrate C9 a, and further a metallayer 40 d is formed inside of the primary groove 38 a.

In FIG. 25C, the primary cap substrate C9 a shown in FIG. 25B is bondedto the base substrate B5 shown in FIG. 25A. For example, the primary capsubstrate C9 a and the base substrate B5 are bonded to each other by asilicon direct bonding technique, which is conducted at a lowtemperature in a vacuum state.

In FIG. 25D, the primary cap substrate C9 a is grinded from the top to aposition where the primary groove 38 a penetrates through the primarycap substrate C9 a. In this way, the groove 38 of the semiconductordevice 120 is formed. The cap substrate C9 is provided by the primarycap substrate C9 a, which is divided into the multiple partial regionsCe by the groove 38, and the metal part 40 as the element of the leadingelectrode De8 is provided by the metal layer 40 d.

Next, in FIG. 26B, the primary base substrate B6 a, which has beenformed to have the acceleration sensor element as shown in FIG. 26A, isturned upside down and bonded to the cap substrate C9.

Then, in FIG. 26C, wiring processing for making electrical connectionsis conducted in the primary base substrate B6 a, and thus the basesubstrate B6 is finished.

In this way, the semiconductor device 120 shown in FIG. 24 ismanufactured.

As described in the above, the primary groove 38 a is formed in theprimary cap substrate C9 a in the cap substrate forming step. Then, themetal layer 40 d is formed on the side wall of the primary groove 38 a,as a part of the leading electrode forming step, to form a primaryleading electrode De8 a. In a substrate bonding step shown in FIG. 25C,the base substrate B5 and the primary cap substrate C9 a are bonded insuch a manner that the opening of the primary groove 38 a is opposed tothe upper surface of the base substrate B5. After the substrate bondingstep, as shown in FIG. 25D, the primary cap substrate C9 a is grindedfrom the top, that is, from a side opposite to the base substrate B5, tomake the cap substrate C9. Thus, the primary leading electrode De8 a andthe primary groove 38 a, respectively, become the leading electrode De8and the groove 38. The metal layer 40 d formed on the side wall of theprimary groove 38 a becomes the metal part 40 of the leading electrodeDe8.

In each of the above-described semiconductor devices 100, 110 to 114 and120 as examples of the semiconductor device according to the embodiment,the cap substrate C4 to C10 is bonded to the base substrate B4 to B6 toprotect the base substrate B4 to B6. Further, the leading electrode De1to De8 for making the electrical connection with the external part atthe end thereof is formed such that the resistance of the leadingelectrode De1 to De8 is reduced and the parasitic capacitance around theleading electrode De1 to De8 will not be easily formed.

The above-described semiconductor devices 110, 110 to 114 and 120 asexamples of the semiconductor device according to the embodiment eachhas the mechanical quantity sensor element for detecting accelerationand/or angular velocity. As another example, the semiconductor deviceaccording to the embodiment can have pressure sensor element, microelectro mechanical system (MEMS) resonator, infrared radiation sensorelement, or any other semiconductor sensor element.

FIG. 27 is a schematic cross-sectional view of a semiconductor device130 having a pressure sensor element PS as an example of thesemiconductor device according to the embodiment. In FIG. 27, partssimilar to the preceding parts are denoted with like referencecharacters.

The semiconductor device 130 has a base substrate B7. The base substrateB7 includes a single crystal silicon substrate 25. The thin singlecrystal silicon layer 24 having different conductivity types is formedat an upper surface layer of the single crystal silicon substrate 25. Adeep, groove 26 is formed at a predetermined region R2 of the basesubstrate B7. The groove 26 extends from a bottom surface to an uppersurface of the single crystal silicon substrate 25, and a membrane Me isformed above the groove 26. The single crystal silicon layer 24 hasmultiple impurity diffused regions (base semiconductor regions) Bd,which are insulated and separated from adjacencies by PN-junctionseparation, in the predetermined region R2.

The membrane Me also has impurity diffused regions Bd1, Bd2. Theimpurity diffused regions Bd1, Bd2 serve as a pressure sensor elementPS. That is, in the semiconductor device 130, the membrane Me displacesin accordance with pressure applied through the groove 26. Thus, achange in resistance of the impurity diffused regions Bd1, Bd2 inaccordance with the displacement is measured to detect the appliedpressure.

Also in the semiconductor device 130, a cap substrate C11 is bonded tothe base substrate B7 made of silicon at the bonding surface D1 and asealed space is formed above the membrane Me. The semiconductor device130 has a leading electrode De9 constructed of the metal part 40. Alower end of the leading electrode De9 connects to an impurity diffusedregion (base semiconductor region) Bd3 of the base substrate B7. Theleading electrode De9 extends from the upper surface of the basesubstrate B7 to the upper surface of the cap substrate C4 through thegroove 35 of the cap substrate C11. For example, an upper end of themetal part 40 is located higher than the upper surface of the capsubstrate C11. The bonding wire 60 is connected to an upper end of theleading electrode De9.

FIGS. 28A to 28D and FIGS. 29A to 29D are schematic cross-sectionalviews for showing a process of manufacturing the semiconductor device130 shown in FIG. 27.

In FIG. 28A, the base substrate 87 is formed. Specifically, the thinsingle crystal silicon layer 24 having the different conductivity typesis formed at the upper surface layer of the single crystal siliconsubstrate 25.

In FIG. 18B, structures such as the impurity diffused regions (basesemiconductor regions) Bd, Bd1 to Bd3 as shown in FIG. 27, except thegroove 26, are formed in the predetermined region R2 of the singlecrystal silicon layer 24.

In FIG. 28C, the cap substrate C11 is formed. For example, theinsulating layer 32 a and the recess 32 b are formed on the lowersurface of the single crystal silicon substrate 30, in the similarmanner as the cap substrate forming process shown in FIGS. 4A to 4C.

In FIG. 28D, the base substrate B7 formed in the step shown in FIG. 28Band the cap substrate C11 formed in the step shown in FIG. 28C arepositioned relative to each other and bonded to each other.

Next, in FIG. 29A, a trench 44 is formed at a predetermined position ofthe cap substrate C11 to reach the impurity diffused region Bd3 of thebase substrate B7.

In FIG. 29B, the metal part 40 is embedded in the trench 44, and thenthe upper surface of the cap substrate C11, that is, the upper surfaceof the single crystal silicon substrate 30 is etched such that the upperend of the metal part 40 is located higher than the upper surface of thecap substrate C11.

In FIG. 29C, a peripheral portion of the trench 44 in which the metalpart 44 has been embedded is etched to form the groove 35.

In FIG. 29D, the bonded base substrate B7 and cap substrate C11 isturned upside down, and the groove 26 is formed from a back side, thatis, from the top in FIG. 29D. Thus, the membrane Me, as a thin membraneportion, is formed. Accordingly, the pressure sensor element PS isformed.

In this way, the semiconductor device 130 shown in FIG. 27 ismanufactured.

Similar to the semiconductor device 100 shown in FIGS. 1A and 1B, thesemiconductor device 130 shown in FIG. 27 has the leading electrode De9constructed of the metal part 40, and the groove 35 is formed betweenthe metal part 40 and the cap substrate C11. The upper end of theleading electrode De9 allows the electrical connection with the externalpart. Therefore, resistance of the leading electrode De9 is reduced, andparasitic capacitance will not be easily formed around the leadingelectrode De9.

The semiconductor device according to the embodiment can be implementedby combining the above described exemplary semiconductor devices invarious ways. Also, as an example of the semiconductor device accordingto the embodiment, a semiconductor device having a chip in which themechanical quantity sensor elements, such as the acceleration sensorelement and the angular velocity sensor element as shown in FIG. 1 andthe pressure sensor element PS as shown in FIG. 27 are formed and theleading electrode constructed of the metal part separated from the capsubstrate by the groove is applicable.

Additional advantages and modifications will readily occur to thoseskilled in the art. The invention in its broader term is therefore notlimited to the specific details, representative apparatus, andillustrative examples shown and described.

1. A semiconductor device comprising: a base substrate made of silicon,the base substrate having a plurality of base semiconductor regions in apredetermined portion of a surface layer thereof, the plurality of basesemiconductor regions being insulated and separated from each other; acap substrate bonded to the predetermined portion of the surface layerof the base substrate; and a leading electrode including a metal part,the leading electrode passing through the cap substrate, the leadingelectrode having a first end connected to one of the plurality of basesemiconductor regions of the base substrate and a second end locatedadjacent to a surface of the cap substrate for allowing an electricalconnection with an external part, the surface being opposite to abonding surface at which the base substrate and the cap substrate arebonded, wherein the leading electrode defines a groove between an outersurface thereof and the cap substrate.
 2. The semiconductor deviceaccording to claim 1, wherein the cap substrate is made of silicon. 3.The semiconductor device according to claim 2, wherein the cap substratehas a plurality of partial regions insulated and separated from eachother, the leading electrode is constructed of the metal part and one ofthe plurality of partial regions, and the metal part is disposed aroundthe one of the plurality of partial regions.
 4. The semiconductor deviceaccording to claim 3, wherein the metal part is disposed to cover an endsurface of the one of the partial regions, the end surface beingadjacent to the second end of the leading electrode.
 5. Thesemiconductor device according to claim 1, wherein the cap substrate ismade of single crystal silicon.
 6. The semiconductor device according toclaim 5, wherein the cap substrate includes a plurality of partialregions insulated and separated from each other, and one of theplurality of partial regions is provided with an integrated circuit. 7.The semiconductor device according to claim 1, wherein the second end ofthe leading electrode is located further from the bonding surface thanthe surface of the cap substrate.
 8. The semiconductor device accordingto claim 7, wherein the second end of the leading electrode has an areagreater than an area of the first end.
 9. The semiconductor deviceaccording to claim 1, further comprising an insulating layer at a bottomportion of the groove to avoid the groove reaching the base substrate.10. The semiconductor device according to claim 1, wherein the capsubstrate is bonded to the predetermined portion of the base substratesuch that a sealed space is provided between the cap substrate and thepredetermined region of the base substrate.
 11. The semiconductor deviceaccording to claim 1, wherein the base substrate includes a SOIsubstrate having an embedded oxide film and a SOI layer along theembedded oxide film, the plurality of base semiconductor regions isprovided by the SOI layer and is insulated and separated from each otherthrough a trench formed in the SOI layer, the trench reaching theembedded oxide film.
 12. The semiconductor device according to claim 1,wherein at least one of the plurality of base semiconductor regionsprovides a fixed semiconductor region including a fixed electrode, atleast another one of the plurality of base semiconductor regionsprovides a movable semiconductor region including a movable electrodeopposed to the fixed electrode and displaceable relative to the fixedelectrode, the movable electrode is formed by conducting a sacrificelayer etching at a portion of the embedded oxide film, the leadingelectrode is connected to each of the fixed semiconductor region and themovable semiconductor region, the fixed semiconductor region and themovable semiconductor region constitute a mechanical quantity sensorelement for detecting a mechanical quantity applied thereto, themechanical quantity being detected based on a change in capacitancebetween the fixed electrode and the movable electrode in accordance witha change in distance between the fixed electrode and the movableelectrode due to the movable electrode being displaced relative to thefixed electrode by the mechanical quantity.
 13. The semiconductor deviceaccording to claim 12, wherein the mechanical quantity includes one ofacceleration and angular velocity.
 14. The semiconductor deviceaccording to claim 1, wherein the base substrate includes a singlecrystal silicon substrate, the plurality of base semiconductor regionsinclude impurity diffused regions that are insulated and separated byPN-junction separation.
 15. The semiconductor device according to claim14, wherein the single crystal silicon substrate has a membrane at asurface portion thereof, at least one of the impurity diffused regionsis disposed in the membrane and constitutes a pressure sensor elementfor detecting a pressure applied to the membrane based on a change inresistance of the impurity diffused region in accordance withdisplacement of the membrane by the pressure.
 16. A method ofmanufacturing a semiconductor device, comprising: forming a basesubstrate made of silicon, wherein the base substrate has a plurality ofbase semiconductor regions in a predetermined portion of a surface layerthereof, the plurality of base semiconductor regions is insulated andseparated from each other; forming a cap substrate; bonding the capsubstrate to the predetermined portion of the base substrate; andforming a leading electrode including a metal part, wherein the leadingelectrode passes through the cap substrate, the leading electrode has afirst end connected to one of the plurality of base semiconductorregions and a second end located adjacent to, a surface of the capsubstrate, and the leading electrode defines a groove between an outersurface thereof and the cap substrate.
 17. The method according to claim16, further comprising: forming a trench in the cap substrate to reachthe one of the plurality of base semiconductor regions after thebonding, wherein the forming of the leading electrode includes embeddinga metal for providing the metal part in the trench and forming thegroove on a periphery of the trench.
 18. The method according to claim16, wherein the forming of the leading electrode is partly conducted inthe forming of the cap substrate so that the leading electrode is formedin condition of being connected to the cap substrate, the bondingincludes connecting the first end of the leading electrode to the one ofthe plurality of base semiconductor regions, and the remainder of theforming of the leading electrode is performed after the bonding.
 19. Themethod according to, claim 16, wherein the forming of the cap substrateincludes forming a primary groove in a primary cap substrate, theforming of the cap substrate further includes forming a primary leadingelectrode, as a part of the forming of the leading electrode, byapplying a metal on a side wall of the primary groove, and the bondingincludes connecting the primary cap substrate to the base substrate suchthat an opening of the primary groove is opposed to the base substrate,the method further comprising: grinding a surface of the primary capsubstrate, the surface being opposite to a bonding surface at which theprimary cap substrate and the base substrate are bonded, so that the capsubstrate is provided by the primary cap substrate, and the leadingelectrode and the groove are respectively provided by the primaryleading electrode and the primary groove.